Title: A Hierarchical Instruction Cache for Ultra-Low-Power Tightly-Coupled Processor Clusters
Researchers from the University of Bologna, ETH Zurich, and GreenWaves Technologies have published a technical paper titled “Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processor Clusters.” This paper addresses the critical requirements of high performance and energy efficiency for Internet of Things (IoT) end-nodes. The researchers propose a hierarchical instruction cache architecture specifically designed for ultra-low-power tightly-coupled processor clusters.
In the realm of IoT, where power consumption is a crucial concern, exploiting tightly-coupled clusters of programmable processors (CMPs) has emerged as a viable solution. However, the instruction cache architecture has been identified as a major bottleneck in terms of timing, bandwidth, and power.
The researchers propose a hierarchical instruction cache tailored to ultra-low-power tightly-coupled processor clusters. This architecture consists of a relatively large cache (L1.5) shared by L1 private caches through a two-cycle latency interconnect. To address the performance loss caused by L1 capacity misses, a next-line prefetcher with cache probe filtering (CPF) from L1 to L1.5 is introduced. Additionally, the core instruction fetch (IF) stage is optimized by removing the critical core-to-L1 combinational path.
Benefits and Results:
The two-level instruction cache architecture provides better scalability than existing shared caches, delivering up to 20% higher operating frequency. On average, it improves maximum performance by up to 17% compared to the state-of-the-art, while maintaining similar energy efficiency for most relevant applications. This solution effectively addresses the criticality of the instruction cache architecture in terms of performance and energy efficiency for parallel ultra-low-power (ULP) clusters.
The hierarchical instruction cache architecture proposed by the researchers offers a promising solution to the challenges faced in achieving high performance and energy efficiency in IoT end-nodes. By optimizing the instruction cache architecture for ultra-low-power tightly-coupled processor clusters, this solution demonstrates significant improvements in operating frequency and performance. As the demand for IoT devices continues to grow, innovative approaches like these will play a crucial role in enabling efficient and powerful IoT systems.
(Note: This article is based on the technical paper titled “Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters” by Chen, Jie, Igor Loi, Eric Flamand, Giuseppe Tagliavini, Luca Benini, and Davide Rossi, published in September 2023.)
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